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5 SCLK Serial Clock
LRCK 6 23 FL
6 LRCK Left/Right Clock
DGND 7 22 AGND
7 DGND Digital Ground
VD 8 21 VA
VL 9 20 AINL+
8 VD Digital Power
MCLK 10 19 AINL-
9 VL Digital Interface Power
SCL/CCLK 11 18 FILT
10 MCLK Master Clock
SDA/CDIN 12 17 AINR-
11 SCL/CCLK Serial Control Interface Clock
AD0/CS 13 16 AINR+
12 SDA/CDIN Serial Control Data I/O
RST 14 15 MUTEC
13 ADO/CS Address Bit 0/ Chip Select
14 RST Reset
15 MUTEC Mute Control
16,17 AINR+,AINR- Differential Analog Inputs
19,20 AINL+,AINL-
18 FILT Internal Voltage Filter
21 VA Analog Power
22 AGND Analog Ground
23,24,25 FR,FL,SR,SL Analog Outputs
26,27,28 SUB,CENTER
74LCX244 (DIC13) : Bus buffer
1. Pin layout
2. Pin function
Pin No. Symbol Function
1G 1 20 Vcc
1 1G Output Enable Input
1A1 2 19 2G
2,4,6,8 1A1 to 1A4 Data Inputs
2Y4 3 18 1Y1
9,7,5,3 2Y1 to 2Y4 Data Outputs
1A2 4 17 2A4
11,13,15 2A1 to 2A4 Data Inputs
17
2Y3 5 16 1Y2
18,16,14 1Y1 to 1Y4 Data Outputs
1A3 6 15 2A3
12
2Y2 7 14 1Y3
19 2G Outputs Enable Input
1A4 8 13 2A2
10 GND Ground(0V)
2Y1 9 12 1Y4
20 Vcc Positive Supply Voltage
GND10 11 2A1
3. Truth table
INPUT OUTPUT
G An Yn
L L L
L H H
H X Z
X:"H"or"L"
Z:High impedance
1-33
TH-A5
VICTOR COMPANY OF JAPAN, LIMITED
AUDIO & COMMUNICATION BUSINESS DIVISION
PERSONAL & MOBILE NETWORK BUSINESS UNIT. 10-1,1chome,Ohwatari-machi,Maebashi-city,371-8543,Japan
200201(V)
(No.21060)
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